Portrait de Warren Gross

Warren Gross

Membre académique associé
Professeur, McGill University, Département de génie électrique et informatique
Sujets de recherche
Apprentissage profond
Optimisation
Théorie de l'information
Traitement du langage naturel

Biographie

Warren Gross est professeur titulaire de la chaire James McGill et directeur du Département de génie électrique et informatique de l'Université McGill. Dans ses recherches, il s’intéresse au rapprochement entre les algorithmes et leur mise en œuvre dans les domaines de l'apprentissage automatique et des communications numériques. Ses travaux portent sur les modèles efficaces d'apprentissage profond, le matériel pour l'apprentissage automatique, l'informatique stochastique, l'exploration matérielle de l'espace de conception pour les réseaux neuronaux, l'apprentissage automatique pour les communications numériques, ainsi que les algorithmes de décodage efficaces et le matériel pour les codes correcteurs d'erreurs.

Étudiants actuels

Publications

Stochastic Decoding of Turbo Codes
Q. Dong
Matthieu Arzel
Christophe Jego
Warren Gross
Stochastic computation is a technique in which operations on probabilities are performed on random bit streams. Stochastic decoding of forwa… (voir plus)rd error-correction (FEC) codes is inspired by this technique. This paper extends the application of the stochastic decoding approach to the families of convolutional codes and turbo codes. It demonstrates that stochastic computation is a promising solution to improve the data throughput of turbo decoders with very simple implementations. Stochastic fully-parallel turbo decoders are shown to achieve the error correction performance of conventional a posteriori probability (APP) decoders. To our knowledge, this is the first stochastic turbo decoder which decodes a state-of-the-art turbo code. Additionally, an innovative systematic technique is proposed to cope with stochastic additions, responsible for the throughput bottleneck.
2010-12-01
IEEE Transactions on Signal Processing (publié)
doi.org
Relaxation Dynamics in Stochastic Iterative Decoders
S. Tehrani
C. Winstead
Warren Gross
Shie Mannor
S. Howard
Vincent C. Gaudet
Stochastic decoding is a recently proposed approach for graph-based iterative error control decoding. We present and investigate three hyste… (voir plus)resis methods for stochastic decoding on graphs with cycles and show their close relationship with the successive relaxation method. Implementation results demonstrate the tradeoff in bit error rate performance with circuit complexity.
2010-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Relaxation Dynamics in Stochastic Iterative Decoders
Saeed Sharifi Tehrani
Chris Winstead
Warren Gross
Shie Mannor
Sheryl L. Howard
Vincent C. Gaudet
Stochastic decoding is a recently proposed approach for graph-based iterative error control decoding. We present and investigate three hyste… (voir plus)resis methods for stochastic decoding on graphs with cycles and show their close relationship with the successive relaxation method. Implementation results demonstrate the tradeoff in bit error rate performance with circuit complexity.
2010-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding
Saeed Sharifi Tehrani
Ali Naderi
Guy-Armand Kamendje
Saied Hemati
Shie Mannor
Warren Gross
This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient high throughput ASIC implementation of stochastic L… (voir plus)ow-Density Parity-Check (LDPC) decoders. The proposed method is applied for ASIC implementation of a fully parallel stochastic decoder that decodes the (2048, 1723) LDPC code from the IEEE 802.3an (10GBASE-T) standard. The decoder occupies a silicon core area of 6.38 mm2 in CMOS 90 nm technology, achieves a maximum clock frequency of 500 MHz, and provides a maximum core throughput of 61.3 Gb/s. The decoder also has good decoding performance and error-floor behavior and provides a bit error rate (BER) of about 4 × 10-13 at Eb/N0=5.15 dB. To the best of our knowledge, the implemented decoder is the most area efficient fully parallel soft -decision LDPC decoder reported in the literature.
2010-09-01
IEEE Transactions on Signal Processing (publié)
doi.org
Majority-Based Tracking Forecast Memories for Stochastic LDPC Decoding
S. Tehrani
Ali Naderi
Guy-Armand Kamendje
Saied Hemati
Shie Mannor
Warren Gross
This paper proposes majority-based tracking forecast memories (MTFMs) for area efficient high throughput ASIC implementation of stochastic L… (voir plus)ow-Density Parity-Check (LDPC) decoders. The proposed method is applied for ASIC implementation of a fully parallel stochastic decoder that decodes the (2048, 1723) LDPC code from the IEEE 802.3an (10GBASE-T) standard. The decoder occupies a silicon core area of 6.38 mm2 in CMOS 90 nm technology, achieves a maximum clock frequency of 500 MHz, and provides a maximum core throughput of 61.3 Gb/s. The decoder also has good decoding performance and error-floor behavior and provides a bit error rate (BER) of about 4 × 10-13 at Eb/N0=5.15 dB. To the best of our knowledge, the implemented decoder is the most area efficient fully parallel soft -decision LDPC decoder reported in the literature.
2010-09-01
IEEE Transactions on Signal Processing (publié)
doi.org
Fully Parallel Stochastic LDPC Decoders
S. Tehrani
Shie Mannor
Warren Gross
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stocha… (voir plus)stic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at Eb/N0=4.25 dB (a bit error rate of 10-8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and IO ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach.
2008-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Fully Parallel Stochastic LDPC Decoders
Saeed Sharifi Tehrani
Shie Mannor
Warren Gross
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stocha… (voir plus)stic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at
2008-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices
S. Tehrani
Christophe Jego
Bo Zhu
Warren Gross
This correspondence extends the application of the recently proposed stochastic decoding approach to decode linear block codes with high-den… (voir plus)sity parity-check matrices and discusses its hardware complexity. Results demonstrate decoding performance close to floating-point iterative soft-input soft-output (SISO) decoding while offering nodes with considerably lower complexity compared to fixed-point SISO decoding.
2008-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices
Saeed Sharifi Tehrani
Christophe Jego
Bo Zhu
Warren Gross
This correspondence extends the application of the recently proposed stochastic decoding approach to decode linear block codes with high-den… (voir plus)sity parity-check matrices and discusses its hardware complexity. Results demonstrate decoding performance close to floating-point iterative soft-input soft-output (SISO) decoding while offering nodes with considerably lower complexity compared to fixed-point SISO decoding.
2008-11-01
IEEE Transactions on Signal Processing (publié)
doi.org