Publications

Computation, Logic, Games, and Quantum Foundations. The Many Facets of Samson Abramsky
Bob. Coecke
Luke Ong
Prakash Panangaden
Samson. Abramsky
2013-01-01
Lecture Notes in Computer Science (publié)
doi.org
Computation, Logic, Games, and Quantum Foundations. The Many Facets of Samson Abramsky
Bob. Coecke
Luke Ong
Prakash Panangaden
Samson. Abramsky
2013-01-01
Computation, Logic, Games, and Quantum Foundations (publié)
doi.org
A Semi-Parallel Successive-Cancellation Decoder for Polar Codes
Camille Leroux
Alexandre J. Raymond
Gabi Sarkis
Warren Gross
Polar codes are a recently discovered family of capacity-achieving codes that are seen as a major breakthrough in coding theory. Motivated b… (voir plus)y the recent rapid progress in the theory of polar codes, we propose a semi-parallel architecture for the implementation of successive cancellation decoding. We take advantage of the recursive structure of polar codes to make efficient use of processing resources. The derived architecture has a very low processing complexity while the memory complexity remains similar to that of previous architectures. This drastic reduction in processing complexity allows very large polar code decoders to be implemented in hardware. An N=217 polar code successive cancellation decoder is implemented in an FPGA. We also report synthesis results for ASIC.
2013-01-01
IEEE Transactions on Signal Processing (publié)
doi.org
A Semi-Parallel Successive-Cancellation Decoder for Polar Codes
Camille Leroux
Alexandre J. Raymond
Gabi Sarkis
Warren Gross
Polar codes are a recently discovered family of capacity-achieving codes that are seen as a major breakthrough in coding theory. Motivated b… (voir plus)y the recent rapid progress in the theory of polar codes, we propose a semi-parallel architecture for the implementation of successive cancellation decoding. We take advantage of the recursive structure of polar codes to make efficient use of processing resources. The derived architecture has a very low processing complexity while the memory complexity remains similar to that of previous architectures. This drastic reduction in processing complexity allows very large polar code decoders to be implemented in hardware. An N=217 polar code successive cancellation decoder is implemented in an FPGA. We also report synthesis results for ASIC.
2013-01-01
IEEE Transactions on Signal Processing (publié)
doi.org
Statistical Language and Speech Processing
Yoshua Bengio
Fethi Bougares
Horia Cucu
Corneliu Burileanu
Myung-Jae Kim
Il-ho Yang
Jordan Rodu
Dean Phillips Foster
Weichen Wu
Stefan Bott
Felix Stahlberg
Luis A. Trindade
Hui Wang
2013-01-01
Lecture Notes in Computer Science (publié)
doi.org
Statistical Language and Speech Processing
Yoshua Bengio
Fethi Bougares
Horia Cucu
Corneliu Burileanu
Myung-Jae Kim
Il-ho Yang
Jordan Rodu
Dean Phillips Foster
Weichen Wu
Stefan Bott
Felix Stahlberg
Luis A. Trindade
Hui Wang
2013-01-01
Lecture Notes in Computer Science (publié)
doi.org
Algorithms in Bioinformatics
P. Agarwal
Tatsuya Akutsu
Amir Amihood
Alberto Apostolico
C. Benham
Gary Gustaf Benson
Mathieu Blanchette
Nadia El-Mabrouk
Olivier Gascuel
Raffaele Giancarlo
R. Guigó
Michael Hallet
D. Huson
G. Kucherov
Michelle R. Lacey
Jens Lagergren
Giuseppe Lancia
Gad M. Landau
Thierry. Lecroq
B. Moret … (voir 21 de plus)
S. Morishita
Elchanan Mossel
Vincent Moulton
Lior S. Pachter
Knut Reinert
I. Rigoutsos
David Sankoff
Sophie Schbath
Eran Segal
Charles Semple
J. Setubal
Roded Sharan
S. Skiena
Jens Stoye
Esko Ukkonen
Lisa Allen Vawter
Alfonso Valencia
Tandy J. Warnow
Lusheng Wang
Rita Casadio
Gene Myers
2012-10-01
Lecture Notes in Computer Science (publié)
doi.org
Theano: Deep Learning on GPUs with Python
James Bergstra
Frédéric Bastien
Olivier Breuleux
Pascal Lamblin
Razvan Pascanu
Olivier Delalleau
Guillaume Desjardins
David Warde-Farley
Ian G Goodfellow
Arnaud Bergeron
Yoshua Bengio
In this paper, we present Theano 1 , a framework in the Python programming language for defining, optimizing and evaluating expressions invo… (voir plus)lving high-level operations on tensors. Theano offers most of NumPy’s functionality, but adds automatic symbolic differentiation, GPU support, and faster expression evaluation. Theano is a general mathematical tool, but it was developed with the goal of facilitating research in deep learning. The Deep Learning Tutorials 2 introduce recent advances in deep learning, and showcase how Theano
2012-01-01
(publié)
www.semanticscholar.org
Delayed Stochastic Decoding of LDPC Codes
Ali Naderi
Shie Mannor
Mohamad Sawan
Warren Gross
A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) dec… (voir plus)oders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93- mm2 and 56.5- mm2 silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at [(Eb)/(No)]=5.5 and 4.8 dB, respectively.
2011-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Delayed Stochastic Decoding of LDPC Codes
Ali Naderi
Shie Mannor
M. Sawan
Warren Gross
A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) dec… (voir plus)oders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93- mm2 and 56.5- mm2 silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at [(Eb)/(No)]=5.5 and 4.8 dB, respectively.
2011-11-01
IEEE Transactions on Signal Processing (publié)
doi.org
Session details: Digital entertainment technologies and arts track posters
Mike Preuss
Christian Gagné
2011-07-12
Proceedings of the 13th annual conference companion on Genetic and evolutionary computation (publié)
doi.org
Session details: Digital entertainment technologies and arts track papers
Mike Preuss
Christian Gagné
2011-07-12
Proceedings of the 13th annual conference on Genetic and evolutionary computation (publié)
doi.org