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Christophe Dubach

Affiliate Member
Assistant Professor, McGill University, School of Computer Science
MILA
Research Topics
Optimization

Biography

Christophe Dubach is an assistant professor jointly appointed to the Department of Electrical and Computer and the School of Computer Science at McGill University in January 2020. Prior to that, he was a reader (associate professor) at the University of Edinburgh.

Dubach’s research interests include data-parallel language design and implementation, high-level code generation and optimization for parallel hardware (e.g., GPUs, FPGAs), architecture design space exploration, and the use of machine-learning techniques applied to all of these areas.

Current Students

Shakiba Bolbolian Khah
PhD - McGill University
Louis Hildebrand
Master's Research - McGill University
Github
Yuan-Po Teng
PhD - McGill University
Jonathan Van der Cruysse
PhD - McGill University
Website
Github

Publications

Mapping parallelism in a functional IR through constraint satisfaction: a case study on convolution for mobile GPUs
Naums Mogers
Li Li
Valentin Radu
Christophe Dubach
Graphics Processing Units (GPUs) are notoriously hard to optimize for manually. What is needed are good automatic code generators and optimi… (see more)zers. Accelerate, Futhark and Lift demonstrated that a functional approach is well suited for this challenge. Lift, for instance, uses a system of rewrite rules with a multi-stage approach. Algorithmic optimizations are first explored, followed by hardware-specific optimizations such as using shared memory and mapping parallelism. While the algorithmic exploration leads to correct transformed programs by construction, it is not necessarily true for the latter phase. Exploiting shared memory and mapping parallelism while ensuring correct synchronization is a delicate balancing act, and is hard to encode in a rewrite system. Currently, Lift relies on heuristics with ad-hoc mechanisms to check for correctness. Although this practical approach eventually produces high-performance code, it is not an ideal state of affairs. This paper proposes to extract parallelization constraints automatically from a functional IR and use a solver to identify valid rewriting. Using a convolutional neural network on a mobile GPU as a use case, this approach matches the performance of the ARM Compute Library GEMM convolution and the TVM-generated kernel consuming between 2.7x and 3.6x less memory on average. Furthermore, a speedup of 12x is achieved over the ARM Compute Library direct convolution implementation.
2022-03-17
Proceedings of the 31st ACM SIGPLAN International Conference on Compiler Construction (published)
doi.org
Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators
Christof Schlaak
Tzung-Han Juang
Christophe Dubach
2022-01-30
ACM Transactions on Architecture and Code Optimization (published)
doi.org
GPU acceleration of finite state machine input execution: Improving scale and performance
Vanya Yaneva
Ajitha Rajan
Christophe Dubach
Model‐based development is a popular development approach in which software is implemented and verified based on a model of the required s… (see more)ystem. Finite state machines (FSMs) are widely used as models for systems in several domains. Validating that a model accurately represents the required behaviour involves the generation and execution of a large number of input sequences, which is often an expensive and time‐consuming process. In this paper, we speed up the execution of input sequences for FSM validation, by leveraging the high degree of parallelism of modern graphics processing units (GPUs) for the automatic execution of FSM input sequences in parallel on the GPU threads. We expand our existing work by providing techniques that improve the performance and scalability of this approach. We conduct extensive empirical evaluation using 15 large FSMs from the networking domain and measure GPU speed‐up over a 16‐core CPU, taking into account total GPU time, which includes both data transfer and kernel execution time. We found that GPUs execute FSM input sequences up to 9.28× faster than a 16‐core CPU, with an average speed‐up of 4.53× across all subjects. Our optimizations achieve an average improvement over existing work of 58.95% for speed‐up and scalability to large FSMs with over 2K states and 500K transitions. We also found that techniques aimed at reducing the number of required input sequences for large FSMs with high density were ineffective when applied to all‐transition pair coverage, thus emphasizing the need for approaches like ours that speed up input execution.
2021-10-07
Software Testing, Verification and Reliability (published)
doi.org