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2021-01
Training Binarized Neural Networks using Ternary Multipliers
Hardware-Aware Design for Edge Intelligence
2020-12
Decoding Polar Codes with Reinforcement Learning
2020-11
2020-10
Neural Successive Cancellation Flip Decoding of Polar Codes
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic
A Regression-Based Method to Synthesize Complex Arithmetic Computations on Stochastic Streams
Towards Efficient On-Chip Learning using Equilibrium Propagation
High-Throughput VLSI Architecture for GRAND
2020-09
Practical Dynamic SC-Flip Polar Decoders: Algorithm and Implementation
2020-08
Introduction to Dynamic Stochastic Computing
2020-07
High-Throughput VLSI Architecture for GRAND.
2020-06
Operation Merging for Hardware Implementations of Fast Polar Decoders
Fast Thresholded SC-Flip Decoding of Polar Codes
2020-05
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning
Simplified Dynamic SC-Flip Polar Decoding
2020-04
High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed–Solomon Codes for Short-Reach Optical Communications
2020-03
Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks
2020-02
Deep Learning Techniques for Decoding Polar Codes
An Efficient Software Stack Sphere Decoder for Polar Codes
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